Method for producing a spacer structure

ABSTRACT

A method for fabricating a spacer structure includes: forming a gate insulation layer having a gate deposition-inhibiting layer, a gate layer and a covering deposition-inhibiting layer on a semiconductor substrate, and patterning the gate layer and the covering deposition-inhibiting layer in order to form gate stacks. An insulation layer is deposited selectively using the deposition-inhibiting layers, thereby permitting highly accurate formation of the spacer structure.

This application is the national stage application of internationalapplication number PCT/DE2003101551, filed on May 14, 2003, which claimsthe benefit of priority to German Patent Application DE 102 269 14.9,filed on Jun. 17, 2002, which is incorporated herein by reference.

The present invention relates to a method for fabricating a spacerstructure, and in particular to a method for fabricating a spacerstructure for field-effect transistors in a sub-100 nanometer range.

During the fabrication of field-effect transistors, as are used, forexample, in MOS transistors but also in nonvolatile memory transistors,what are known as spacer structures or side wall insulations are used inparticular for sufficient insulation of what are known as gate stacksand for the self-aligning formation of source/drain regions.

FIGS. 1A and 1B show simplified sectional views to illustratesignificant fabrication steps involved in the fabrication of a spacerstructure in accordance with the prior art. In accordance with FIG. 1A,during this process gate stacks G having a gate insulation layer 200 anda control or gate layer 300 above it are formed on a support substrate100, which usually consists of a semiconductor material. Then, aninsulation layer 400 is deposited with a substantially constantthickness, i.e. conformally, on the surface on the support substrate 100and of the gate stacks G.

In accordance with FIG. 1B, in a subsequent fabrication step anisotropic etching process is carried out, such as for example reactiveion etching (RIE), resulting in the final spacer structure S400 whichallows sufficient insulation or sufficient protection of the gate stacksG and, furthermore, allows self-aligning formation of the source/drainregions S and D in the support substrate 100, for example by means ofion implantation (not shown).

However, a drawback of a conventional method of this type forfabricating spacer structures is that control of the dimensions of thespacers S400 is inadequate. More specifically, the conformal depositionon the gate stacks G alone results in significant fluctuations inthickness between different spacers S400, and the use of reactive ionetching (RIE) also entails a risk of damage to a gate insulation layeror a gate oxide. Furthermore, there are in some cases considerablefluctuations in etching rate, which are dependent on a particularposition on the wafer and on the spatial density of the gates. This inturn results in spacer structures of different thicknesses.

Particularly for the fabrication of field-effect transistors in asub-100 nanometer range, which will be carried out as standard in thenear future, however, fluctuations of this type in the spacer structuresused will not be tolerable. The reasons for this are firstly that theminimum distance between adjacent gate stacks G is reduced in the sameway, resulting in considerable problems during the deposition ofinsulation layers and etching clear of the support substrate. Sincethese spacer structures therefore act as self-aligning masks for thedimensions of implanted source/drain regions, conventional fabricationmethods of this type for producing spacers can no longer be used inparticular for feature sizes of the order of magnitude of 30 nanometers.In this respect, in particular the difficulties with lithography, theetching of the gate stack and the etching of the actual spacers shouldbe mentioned.

The invention is therefore based on the object of providing a method forfabricating a spacer structure which has an increased level of accuracy.

For the first time, it is possible to form spacer structures even in asub-100 nanometer range in a manner which can be controlled easily andwith a high level of accuracy in particular by forming a gate insulationlayer, a gate layer and a covering deposition-inhibiting layer on asemiconductor substrate, the gate insulation layer having a gatedeposition-inhibiting layer, by subsequently patterning the gate layerand the covering deposition-inhibiting layer in order to form gatestacks and finally depositing an insulation layer selectively withrespect to the deposition-inhibiting layers in the gate insulation layerand on the gate layer. The omission of the reactive ion etching processwhich is customarily used furthermore means that there is no risk ofdamage to the sensitive gate insulation layers.

In a further step, it is preferable to carry out an implantation inorder to form lightly doped doping regions in the semiconductorsubstrate, so that a channel length can be set very accurately and in aself-aligning manner using the spacer structure.

In a further step, it is preferably possible to produce a furtherinsulation layer selectively with respect to the deposition-inhibitinglayers in order to form a widened spacer structure and to carry out afurther implantation in order to form source/drain regions in thesemiconductor substrate, resulting in a spacer structure with improvedinsulation properties which is suitable for forming the connectionregions of a respective field-effect transistor in a self-aligningmanner.

The deposition-inhibiting layers preferably comprise a nitride layerand/or an oxynitride layer with a high nitrogen content, in which caseozone-enhanced TEOS deposition is carried out during the selectiveformation of the insulation layer. In this case, not only is aparticularly high-quality gate dielectric obtained, but also aparticularly high selectivity is achieved during the deposition usingstandard materials.

The thin residual layers formed on the deposition-inhibiting layersduring the selective deposition can optionally be removed by wetetching, with the result that contact openings for the source/drainregions and the gate layer can be formed in a particularly simple way.

To further improve the electrical properties of the spacer structure,the selectively deposited insulation layer can be thermally annealed andthereby densified.

In a further step, it is preferable for the deposition-inhibiting layersto be removed in order to uncover the gate layer and the source/drainregions in the semi-conductor substrate, for a material which can besilicided to be deposited over the entire surface and then for a surfacelayer of the uncovered semiconductor substrate and the gate layer to beconverted using the material which can be silicided in order to formhighly conductive connection regions.

The invention is described in more detail below on the basis of anexemplary embodiment and with reference to the drawing, in which:

FIGS. 1A and 1B show simplified sectional views in order to illustratesignificant fabrication steps in the fabrication of a spacer structurein accordance with the prior art; and

FIGS. 2A to 2F show simplified sectional views to illustrate significantfabrication steps in the fabrication of a spacer structure according tothe invention.

FIGS. 2A to 2F show simplified sectional views to illustrate significantfabrication steps in the fabrication of a spacer structure in accordancewith the present invention, reference being made, for example, to astandard process for the fabrication of CMOS transistors.

Accordingly, it is first of all possible to form active regions (notillustrated), for example by means of an STI (shallow trench isolation)process, in a support substrate 1, which preferably consists of asilicon semiconductor substrate. Then, to produce a gate insulationlayer 2 having at least one gate deposition-inhibiting layer 2A, anitride layer, such as for example Si₃N₄, and/or an oxynitride layerwith a high nitrogen content (SiON) is formed, for example, by means ofa deposition process on the support substrate 1. Alternatively, inaccordance with FIG. 2A, this gate insulation layer 2 may also comprisea multiple layer comprising the gate deposition-inhibiting layer 2Adescribed above (nitride layer and/or oxynitride layer with a highnitrogen content) and an oxide layer 2B, such as for example SiO₂. Inthis way, improved charge retention properties can be produced inparticular in the region of nonvolatile semiconductor memory components.

Then, as shown in FIG. 2A, a control or gate layer 3 is formed, thispreferably involving the deposition of semiconductor material(polysilicon or poly-SiGe) in a thickness of approx. 100 to 150nanometers.

Furthermore, a covering deposition-inhibiting layer 4, which in the sameway as the gate deposition-inhibiting layer 2A includes a nitride layerand/or an oxynitride layer with a high nitrogen content, is formed atthe surface of the gate layer 3.

It is preferable for an approximately 5 to 10 nanometer thick siliconnitride layer 4, to be deposited at the surface of the gate layer 3 bymeans of an LPCVD process (low pressure chemical vapour depositionprocess). To pattern the layer sequence comprising the layers 3 and 4,by way of example it is possible to form a hard mask layer 5 at thesurface of the covering deposition-inhibiting layer 4, in which case, byway of example, an approximately 50 nanometer thick TEOS layer isdeposited as an oxide hard mask.

The actual patterning then takes place using, for example,photolithographic processes which are conventional and are therefore notillustrated, involving the application of a resist material, exposureand patterning of this material and then first of all patterning of thehard mask 5 using the patterned resist. Then, the resist is removed orstripped and the actual patterning of the layers 3 and 4 is carried outusing the patterned hard mask 5 to form gate stacks G, the gatedeposition-inhibiting layer 2A also being used as an etching stop layer.In this case, it is customary to use an anisotropic etching process,with the hard mask 5 ultimately being removed, resulting in thesectional view illustrated in FIG. 2B.

Then, in accordance with FIG. 2C, an insulation layer 6 is depositedselectively with respect to the gate deposition-inhibiting layer 2Abetween the gate stacks G and the covering deposition-inhibiting layer 4on the gate stacks G. Particularly in the case of the nitride and/oroxynitride layers which are preferably used, an oxide depositionachieves selectivities in a range from 5 to 10, and consequently highoxide growth is established at the side walls of the gate stacks G,while only slight oxide growth is observed at the horizontal surface ofthe deposition-inhibiting layers 2A and 4. Using a selective oxidedeposition of this type, it is possible for spacer structures with athickness of, for example, 12 to 15 nanometers to be produced highlyaccurately and in a manner which can be controlled easily, with theresult that it is now possible for even field-effect transistors in thesub-100 nanometer range to be produced in a simple and accurate way. Inparticular, however, there is no need to use any additional anisotropicetching processes, such as for example reactive ion etching (RIE), inthis fabrication method, and consequently it is reliably possible toprevent the sensitive gate insulation layers from being damaged ordestroyed.

Then, in accordance with FIG. 2C, in an optional implantation step it ispossible to form lightly doped connection doping regions LDD using theselectively deposited insulation layer 6 in a self-aligning manner inthe semiconductor substrate 1, with the result that effective channellengths can be set highly accurately in particular with very smallfeature sizes of less than 100 nanometers.

For the selective deposition of the insulation layer 6 it is preferableto use an ozone-enhanced TEOS deposition process which can be carriedout in a conventional chemical vapour deposition apparatus and can beimplemented using an ozone-activated TEOS (tetraethyl orthosilicate).The growth of the insulation layer 6 or of the TEOS is in this casehighly dependent on the uncovered silicon surfaces. Accordingly,significantly less TEOS growth takes place at the deposition-inhibitinglayers 2A and 4, which in the case of nitride layers amounts toapproximately one fifth of the growth on pure silicon.

The result is preferably a TEOS layer with a highly homogenous siliconoxide layer without deviations in the stoichiometry as a result of a gasflow ratio of the TEOS to ozone being very high at the start of a vapourdeposition and subsequently being varied until an equilibrium state isestablished in which the gas flow ratio of TEOS to ozone is low.

By way of example, the gas flow ratio of TEOS to the ozone-containinggas is 10, while, in the stable or steady state of the gas flow ratioafter about one minute, this ratio is 0.4. To determine the preciseparameters, reference is made to “N. ELBEL, Z. GABRIC et al.: A new STIprocess spaced on selective oxide deposition, reported at the 1998symposium on VLSI technology, Honolulu, Hi.”, which describes a SELOXdeposition process of this type.

This method advantageously also reduces the thickness of thedeposition-inhibiting layers 2A and 4, with the result that these layersare easier to remove at a later stage. Since a method of this type alsotakes place at temperatures of between 350 degrees Celsius and 600degrees Celsius, it is possible to keep the thermal loads on thesemiconductor circuits to be formed at a low level in particular in alower temperature range.

It is optionally possible, in accordance with FIG. 2C, to carry out whatis known as a densification anneal or an additional oxidation step todensify the selectively deposited insulation layer 6, and in this waythe electrical properties and in particular the insulation properties ofthis layer can be improved further.

The result is a spacer structure which can be set highly accurately evenin a sub-100 nanometer range, with thickness changes along the sidewalls only being in the range from 5 to 7%, while the crystallographicorientations in the substrate 1 and in the gate layer 3 are highlyindependent of one another.

In addition to the spacer structure which is illustrated in FIG. 2C andis already eminently satisfactory, this structure can also be modifiedor widened. For example, the selectively deposited insulation layer canbe partially etched by means of a conventional wet-etching process insuch a manner that the very thin residual layers formed at thedeposition-inhibiting layers 2A and 4 are completely removed and in thisway the gate deposition-inhibiting layer 2A and the coveringdeposition-inhibiting layer 4 are uncovered.

In accordance with FIG. 2D, it is in addition possible for one orfurther insulation layer(s) 7 to be deposited, once again selectivelywith respect to the deposition-inhibiting layers 2A and 4, a thickeroxide layer, preferably an oxide layer which is approximately 30 to 50nanometers thick, then being formed at the side walls of the gate stacksG. The selective deposition process illustrated in FIG. 2D once againsubstantially corresponds to the selective deposition process shown inFIG. 2C, and consequently the description of this process will not berepeated below.

In accordance with FIG. 2D, following optional removal of the residuallayers on the gate deposition-inhibiting-layer 2A and the coveringdeposition-inhibiting layer 4, it is once again possible to carry out afurther implantation I2 in order to form the actual source/drain regionsS/D in the semiconductor substrate 1, resulting in reduced resistancesin the source/drain regions and improved electrical properties for thespacer structure comprising the insulation layers 6 and 7. Once again, athermal anneal can be carried out in order to improve the electricalproperties of the spacer structure, with the result that the depositedoxide is densified and the damage caused in the substrate 1 as a resultof the implantation is annealed.

In accordance with FIG. 2E, in a subsequent step, by way of example, awet etch is carried out, with the result that the deposition-inhibitinglayers 2A and 4 are removed and the semiconductor substrate 1 and thegate layer 3 are uncovered. If the nitride layer and/or oxynitride layeris used as deposition-inhibiting layer 2A and/or 4, it is preferable tocarry out a nitride wet-etching process.

In accordance with FIG. 2F, to further improve the electricalconductivities of the gate layer 3 and of the source/drain regions S/Dand/or to produce highly conductive connection regions, it is optionallypossible first of all to deposit material which can be silicided or ametal layer which can be silicided, such as for example cobalt, nickelor platinum, over the entire surface. Then, the crystalline surfacelayer of the semiconductor substrate 1 or the polycrystalline surfacelayer of the gate layer 3 is converted, using the material which can besilicided, in order to form highly conductive connection regions 8, thismaterial not forming a silicide at those surfaces which are not incontact with the semiconductor material (silicon), but rather thematerial which has been deposited (metal) remaining in place, for whichreason selective back-etching of the deposited layer can once again becarried out by means of a preferably wet-chemical etching process. Inthis way, it is possible to carry out a multiplicity of patterning stepsusing only a single etching chamber in order to form the spacerstructures and the connection regions, which means that the fabricationcosts are reduced further.

If cobalt, nickel or platinum is used, the highly conductive connectionregions 8 which result are cobalt, nickel or platinum silicide layers,which can be formed in a self-aligning manner by means of the spacerstructures which have been formed in the novel way.

The transistor structure is completed in the usual way, and consequentlythese steps do not need to be explained in more detail below.

The invention has been described above on the basis of a CMOS transistorbut is not restricted to this particular application and also in thesame way encompasses other semiconductor components which havefield-effect transistors with spacer structures, such as for examplenonvolatile semiconductor memory components.

Furthermore, the invention is not restricted to the nitride and/oroxynitride layers described as deposition-inhibiting layers incombination with the Selox process described, but rather in the same wayalso encompasses alternative deposition-inhibiting layers and associatedselective deposition processes.

LIST OF REFERENCE SYMBOLS

-   1, 100 Semiconductor substrate-   2, 200 Gate insulation layer-   3, 300 Gate layer-   2A Gate deposition-inhibiting layer-   2B Oxide layer-   4 Covering deposition-inhibiting layer-   400 Insulation layer-   S400 Conventional spacer structure-   5 Hard mask layer-   6, 7 Selectively deposited insulation layer-   S6, S7 Spacer structure-   8 Connection region-   I1, I2 Ion implantation-   G Gate stack-   S source region-   D drain region-   LDD connection doping region

1. A method for fabricating a spacer structure, the method comprising:a) forming a gate insulation layer having a gate deposition-inhibitinglayer, a gate layer and a covering deposition-inhibiting layer on asemiconductor substrate, wherein the gate deposition-inhibiting layerand the covering deposition-inhibiting layer include at least one of anitride layer and an oxynitride layer; b) patterning the gate layer andthe covering deposition-inhibiting layer in order to form gate stacks;and c) depositing an insulation layer selectively with respect to thedeposition-inhibiting layers to form the spacer structure; d) carryingout an implantation in order to form connection doping regions in thesemiconductor substrate; e) depositing a further insulation layerselectively with respect to the deposition-inhibiting layers in order toform a widened spacer structure; and f) carrying out a furtherimplantation in order to form source/drain regions in the semiconductorsubstrate.
 2. The method according to claim 1, wherein the at least oneof nitride layers and oxynitride layers have high nitrogen content, andozone-enhanced TEOS deposition is carried out in.
 3. The methodaccording to claim 1, wherein the selectively deposited insulationlayers side walls of the gate stack have spacer layers and at thedeposition-inhibiting layers have thin residual layers, the methodcomprising removing the residual layers by wet etching.
 4. The methodaccording to claim 1, further comprising densifying the selectivelydeposited Insulation layers.
 5. The method according to claim 1, furthercomprising: g) removing the deposition-inhibiting layers in order touncover the gate layer and the semiconductor substrate; h) depositing amaterial which can be silicided; and i) converting a surface layer ofthe uncovered semiconductor substrate and the gate layer using thematerial which can be silicided in order to form highly conductiveconnection regions for source/drain regions and the gate layer.
 6. Themethod according to claim 1, wherein the gate layer includespolycrystalline silicon and the semiconductor substrate includescrystalline silicon.
 7. The method according to claim 1, wherein thedeposition-inhibiting layers include at least one of nitride layers andoxynitride layers with a high nitrogen content, and ozone-enhanced TEOSdeposition is carried out in at least one of step c) and step e).
 8. Themethod according to claim 1, further comprising densifying one of theselectively deposited insulation layers in c) or e).
 9. A method offabricating a sub-100 nanometer field-effect transistor, the methodcomprising fabricating a spacer structure, fabrication of the spacerstructure comprising: a) forming a gate insulation layer having a gatedeposition-inhibiting layer, a gate layer and a coveringdeposition-inhibiting layer on a semiconductor substrate; b) patterningthe gate layer and the covering deposition-inhibiting layer in order toform gate stacks; c) depositing an insulation layer selectively withrespect to the deposition-inhibiting layers to form the spacerstructure; d) carrying out an implantation in order to form connectiondoping regions in the semiconductor substrate; e) depositing a furtherinsulation layer selectively with respect to the deposition-inhibitinglayers in order to form a widened spacer structure; and f) carrying outa further implantation in order to form source/drain regions in thesemiconductor substrate, wherein the gate deposition-inhibiting layerand the covering deposition-inhibiting layer include at least on of anitride layer and an oxynitride layer.
 10. The method according to claim9, wherein the at least one of nitride layers and oxynitride layers havea high nitrogen content, and ozone-enhanced TEOS deposition is carriedout in c).
 11. The method according to claim 9, wherein the selectivelydeposited insulation layers at side walls of the gate stack have spacerlayers and at the deposition-inhibiting layers have thin residuallayers, the method comprising removing the residual layers by wetetching.
 12. The method according to claim 9, further comprisingdensifying the selectively deposited insulation layer.
 13. The methodaccording to claim 9, further comprising: g) removing thedeposition-inhibiting layers in order to uncover the gate layer and thesemiconductor substrate; h) depositing a material which can besilicided; and i) converting a surface layer of the uncoveredsemiconductor substrate and the gate layer using the material which canbe silicided in order to form highly conductive connection regions forsource/drain regions and the gate layer.
 14. The method according toclaim 9, wherein the gate layer includes polycrystalline silicon and thesemiconductor substrate includes crystalline silicon.
 15. The methodaccording to claim 9, wherein the at least one of nitride layers andoxynitride layers have a high nitrogen content, and ozone-enhanced TEOSdeposition is carried out in at least one of step c) and step e). 16.The method according to claim 9, further comprising densifying one ofthe selectively deposited insulation layers in c) or e).